Model for Predicting Fatigue Life of Nanomaterials

Model for Predicting Fatigue Life of Nano genuinesIntroductionIn the past, the primary function of micro-systems advancement was to pop the question input/output (I/O) connections to and from integ pastured circuits (ICs) and to supply interconnection between the components on the system circuit card level speckle physically supporting the electronic device and protecting the assembly from the environment.In order to increment the functionality and the miniaturization of the current electronic devices, these IC devices tole localize not only incorpo enjoind much junction transistors but swallow in any case included more active and passive components on an individual crisp. This has resulted in the emerging trend of a new confluent system1Currently, there be terce main approaches to achieving these oblique systems, namely the system-on- check (SOC), system-in-package (SIP) and system on package (SOP). SOC seeks to integ stray numerous system functions on one te lam . However, this approach has numerous fundamental and economical limitations which include high fabrication costs and desegregation limits on wireless communications, which over delinquent to inherent losses of ti and coat restriction.SIP is a 3-D advancement approach, where vertical stacking of multi- micro chip modules is employed. Since all of the ICs in the stack argon still limited to CMOS IC processing, the fundamental integration limitation of the SOC still remains. SOP on the other hand, seeks to achieve a highly integrated microminiaturized system on the package exploitation te for transistor integration and package for RF, digital and optical integration1 IC packaging is one of the key enabling technologies for microprocessor performance.As performance ontogenys, technical challenges ontogeny in the argonas of effect delivery, heat removal, I/O parsimony and thermo- mechanic reliability. These are the nearly difficult challenges for improving performance and i ncreasing integration, along with decreasing manufacturing cost.Chip-to-package interconnections in microsystems packages serve as electrical interconnections but often fail by mechanisms such as bust and creep. Furthermore, driven by the need for development the system functionality and decrease the blow surface, the International Technology Roadmap for Semi-conductors (ITRS) has predicted that integrated chip (IC) packages provide re discrepancy interconnections with I/O pitch of 90 nm by the year 2018 2. Lead-based conjoin temporals read been utilize for interconnections in flip chip technology and the surface mount technology for many decades.The traditional lead-based and lead-free solder bumps bequeath not match the thermal mechanized requirement of these fine pitches interconnects. These electronic packages, even under normal operating conditions, provoke reach a temperature as high as one hundred fiftyC. Due to differences in the coefficient of thermal expans ion of the substantives in an IC package, the packages will experience signifi passelt thermal argumentations due to the mismatch, which in turn will stir lead and lead-free solder interconnections to fail prematurely.Aggarwal et al 3 had modeled the foc utilize experienced by chip to package interconnect. In his field of study, he developed interconnects with a height of 15 to 50 micrometre on different substrate using classic beam theory. sign 1 shows the schematic of his model and a thick of some of his results.Although compliant intrerconect could cut offs the tautness experienced by the interconnect, it is still in sufficient. Chng et al. 4 performed a parametric study on the bust life of a solder column for a pitch of 100micrometre using a macro-micro approach. In her do, she developed models of a solder column/bump with a pad coat of 50micrometre and highschool of 50 micrometre to 200 micrometre. Table I shows a abbreviation of some of her results.Table 1.1 Fati gue life estimation of solder columnchip oppressiveness (micrometre)250640640640 menu CTE (ppm/K)1818105solder column height (micrometre)Fatigue life estimation/cycle)5081N.A1713237100cl27276312415013431518440520074382735772It atomic number 50 be seen from Table 1.1 that the harass lives of all solder columns are extremely short. by from the 5ppm/K board where there is excellent CTE matching, the largest labour life of the solder column is only about 518 cycles. As expected, the fatigue life adjoins signifi sterntly when the board CTE decreases from 18ppm/K to 10ppm/K and as the height developments from 50micrometre to 200micrometre.This is mainly due to the large strain induced by the thermal mismatch as shown in icon 1.2.The maximum inelastic principal strain was about 0.16 which exceeds the maximum strain that the veridical can support. Although the fatigue life of the chip to package interconnection can be increases by increasing the interconnects height, it will not be able to meet the high frequency electrical requirements of the future IC where they need to be operating at a high frequencies of 10-20 GHz and a signal bandwidth of 20 Gbps,By definition, nano see-through materials are materials that pass water atom size less than 100nm and these materials are not new since nanotransparent materials keep been discovered in several naturally-occurring specimens including seashells, bone, and tooth enamel 5, 6. However, the nanocrystalline materials fall in been attracting a lot of inquiry interest due to its superior mechanic and electrical properties as compared to the coarse- scintillaed counterpart.For example, the nano-crystalline atomic number 29 has about 6 times the strength of bulk pig 7. Furthermore, the improvement in the mechanic properties due to the diminution in grain size has been well-attested. Increase in strength due to the decrease in grain-size is predicted by the Hall-Petch coitusship which has also been confirme d numerically by Swygenhoven et al 8 and was first show experimentally by Weertman 9.The implantation of nanocrystalline horseshit as interconnect materials seems to be feasible from the processing viewpoint too. Copper has been social functiond as interconnects materials since 1989 whereas nano- hair has also been widely processed using electroplating and other sober plastic deformation techniques in the past few years. For instance, Lu et al. 10 stick out inform electroplating of nano-copper with grain size less than 100 nm and electrical conductivity comparable to microcrystalline copper. Furthermore, Aggarwal et al 11 have demonstrate the feasibility of using electrolytic capacitor plating processes to deposit nanocrystalline nickel as a back-end wafer compatible process. However, there are certain challenges regarding implantation of nanocrystalline copper as interconnects materials.As discussed above, nanocrystalline copper have a high potential of being apply as the n ext generation interconnect for electronic packaging. However, it is vital to understand their material properties, deformation mechanisms and micro mental synthesiss stability. Although the increase in strength due to the Hall-Petch analogyship which has also been confirmed numerically and experimentally by Weertman 9, the improvement in the fatigue properties is not well put down and no model has been established to predict/characterize these nano materials in interconnection application conflicting results regarding the fatigue properties have also been report. Kumar et al 12 reported that for nano-crystalline and ultra-fine crystalline Ni, although there is an increase in plastic stress range and the endurance limit, the crack step-up rate also increases.However, Bansal et al. 7 reported that with decreasing grain size, the tensile stress range increases but the crack growing rate decreases substantially at the same cyclic stress intensity range. Thus, nano grammatical c onstructiond materials can potentially provide a solution for the reliability of low pitch interconnections. However, the fatigue resistance of nanostructured interconnections needs to be further investigated.Since grain boundaries in polycrystalline material increases the enumerate energy of the system as compare to perfect single crystal, it will resulted in a driving force to tighten the overall grain terminus ad quem area by increasing the average grain size. In the case of nanocrystalline materials which have a high heap fraction of grain boundaries, there is a huge driving force for grain to growth and this presented a presents a significant obstacle to the processing and implement of nanocrystalline copper for interconnect applications.Millet et al 13 have shown, though a series of systematic molecular dynamics simulations, grain growth in bulk nanocrystalline copper during annealing at constant temperature of 800K can be impeded with dopants segregated in the grain boun daries regions. However, it has been notice that stress can trigger grain growth in nanocrystalline materials 14 and there is no writings available on impeding stress assisted grain growth. There is an impending need to investigate the impediment to grain growth shaked by the dopant during fatigue/stress assisted grain growthDissertation ObjectivesThe goal of present project is to develop a model for the fatigue resistance of nano-materials that have been shown to have superior fatigue resistance. Accordingly, the pursuance seek objectives are proposed.Develops a model for predicting fatigue life of nanostructured chip-to-package copper interconnectionsDevelops a fundamental understanding on the fatigue bearing of nanocrystalline copper for interconnect applicationAddresses the issue on the stability of nanocrystalline materials undergoing cyclic loadingoerview of the ThesisThe thesis is organized so that past search on nanocrystalline materials forms the basis of the unders tanding and new knowledge discovered in this research. Chapter 2 reviews much of the pertinent belles-lettres regarding nanocrystalline materials, including synthesis, deformation mechanisms, and grain growth.Chapter 3 describes a detailed overview of the technical aspects of the molecular dynamics simulation method including inter-atomic potentials, time integration algorithms, the NVT NPT, and NEPT ensembles, as well as periodic demarcation conditions and neighbor lists. involve in this chapter is the algorithms for creating nanocrystallinematerials utilise in this dissertations.. Chapter 4 describes the simulation procedure designed to investigate and develop the long crack growth analysis. The results of the long crack growth analysis will be presented at the end of Chapter 4. Chapter 5 presents the result and discussion on mechanical carriage of single and nanocrystalline copper subjected to monotonic and cyclic loading whereas Chapter 6 presents the result and discussion on the impediment to grain growth ca apply by the dopant during fatigue/stress assisted grain growth. Finally, conclusions and recommendations for future work are presented in Chapter 5.Chapter 2This chapter offers an expanded summary of the literature published with regards to the fabrication methods, characterization, and properties of nanocrystalline materials in addition to a description of existing interconnect technology.2.1 Off-Chip interlink TechnologiesChip-to-package interconnections in microsystems packages serve as electrical interconnections but they will often failed by mechanisms such as fatigue and creep. Furthermore, driven by the need for increase the system functionality and decrease the make size, the International Technology Roadmap for Semi-conductors (ITRS) has predicted that interconnections of integrated chip (IC) packages will have a I/O pitch of 90 nm by the year 2018 2.The International Technology Roadmap for Semiconductors (ITRS) roadmap is a roadmap th at semiconductor industry closely follows closely and its projects the need for several technology generations. The package must be capable of meeting these projections in order for it to be successful. This section reviews some of the current interconnect technology.Wire bonding 15 as shown in introduce 2.1, is by and large considered as one of the roughly simple, cost-effective and flexible interconnect technology. The devices on the te die are (gold or aluminum) wire bonded to electrically connect from the chip to the wire bond pads on the periphery. However, the disadvantages of wire bonding are the slow rate, large pitch and long interconnect length and hence this will not be suitable for high I/O application.Instead of wires in the wire bonding, tape automated bonding (TAB) is an interconnect technology using a prefabricated perforated polyimide film, with copper leads between chip and substrate. The advantage of this technology is the high throughput and the high lead cou nt. However, it is limited by the high initial costs for tooling.An pick to peripheral interconnect technology is the area-array solution, as shown in skeletal frame 2.3, that access the unused area by using the area under the chip. In area-array packaging, the chip has an array of solder bumps that are joined to a substrate. Under-fill is then fills the gap between the chip and substrate to enhance mechanical adhesion. This technology gives the highest packaging complicatedness methods and best electrical characteristics of all the avaiable interconnection technology. However, not only is its initial cost is high, it requires a very demanding technology to establish and operate.With the need for higher I/O density, compliant interconnects have been developed to compensate the mechanical requirements of high performance micron sized interconnects. The basic idea is to reduce shear stress experienced by the interconnects through increasing their height or decreasing of its shear modulus (i.e. increases in their compliant) and hence the name compliant interconnects. Some of recent research in compliant interconnects include Tesseras Wide Area upended Expansion, Form Factors Wire on Wafer and Georgia Institute of Technologys Helix interconnects 17-19 as shown in envision 2.4.Although compliant interconnects can solve the problem of mechanical reliability issue, they are done at the expense of the electrical performance. Since there is a need to reduce the packages parasitic through a decrease line delays, there is a need to minimize the electrical connection length in order to increase the system working frequency. Hence, compliant interconnect may not meet the high electrical frequency requirements of future devices. get wind 2.4 (a) Wide Area plumb Expansion, (b) Wire on Wafer and (c) G-Helix 17-19Lead and lead-free solders typically fail mechanical when scaled down to less than to a pitch of 100 mm. Compliant interconnections, on the other hand, do not meet the high frequency electrical requirements. The Microsystems Packaging Research Center at Georgia institute of Technology had demonstrated the feasibility of using re-workable nanostructure interconnections. Aggarwal et al 20 had show that nanostructured nickel interconnections, through a Flip Chip test vehicle, was able to improve the mechanical reliability maculation maintaining the shortest electrical connection length. However, the main disadvantages of this method was the significant signal loss at high frequency signal of nanocrystalline nickel 21.As discussed above, nanostructure interconnects technology is the most promising interconnect technology to best meet the stringent mechanical and electrical requirement of next generation devices. However, there is a need of an switch materials and a sensible choice of materials in this case would be nanocrystalline copper for its high strength material with superior electrical conductivity.Hence, it would be beneficial to us e nanocrystalline-copper as material for the nanostructure interconnects. Due to the tendency for the grain to grow, there is a need to stabilize the grain growth in nanocrystalline copper before using it could be considered as a potential candidate for nanostructure interconnect.2.2 Nanocrystalline materialNanocrystalline materials are polycrystalline materials with an average grain size of less than 100 nm 22. everywhere the past decade , new nanocrystalline or nanostructured materials with key microstructural length scales on the order of a few tens of nanometers has been gaining a lot of interest in the material science research society.This is mainly due to its unique and superior properties, as compared to their microcrystalline counterparts which includes increased strength 22 and wear resistance 23. These unique properties are due to the large flock fraction of atoms at or near the grain boundaries. As a result, these materials have unique properties that are representativ e of both the grain boundary surface characteristics and the bulk.Recent advances in synthesis and processing methodology for producing nanocrystalline materials such as inert blow condensation 24, mechanical milling 25, 26, electro-deposition 27, and gruelling plastic deformation 28 have made it possible to produce sufficient nanocrystalline materials for small scale application.2.2.1 SynthesisInert gas condensation, the first method used to synthesis bulk nanocrystalline 29, consists of evaporating a metal inside a high-vacuum chamber and then backfilling the chamber with inert gas 30. These evaporated metal atoms would then collide with the gas atoms, causing them to lose kinetic energy and con dumbs into powder of small nano-crystals. These powders are then compacted under high pressure and vacuum into nearly fully dense nanocrystalline solids.The grain size distribution obtained from this method is usually very narrow. However, the major draws back of this method are its high porosity levels and imperfection bonding. Grain coarsening also occurs due to the high temperature during the compaction stage 31.Mechanical milling consists of heavy cyclic deformation in powders until the final composition of the powders corresponds to a certain percentages of the individual initial constituents 25, 26. A wide grain size distribution is obtained by this method. This technique is a popular method to prepare nanocrystalline materials because of its applicability to any material and simplicity. However, their main drawback includes contamination and grain coarsening during the consolidation stage.Electro-deposition consists of using electrical current to reduce cations of a desired material from a electrolyte solution and coating a conductive object on the substrate. Electro-deposition has many advantages over processing techniques and this includes its applicability to a wide variety of materials, low initial capital investment requirements and porosity-free sunk products without a need for consolidation processing 27. Furthermore, Shen et al. 32 and Lu et al.33 had recently show that the right electro-deposition condition can produce a highly twinned structure which leads to enhance ductility. The main drawback of this method is it is the difficulty to achieve high purity.Severe plastic deformation, such as high-pressure torsion, equal channel angular bulge (ECAE), continuous confined shear straining and accumulative roll-bonding, uses extreme plastic straining to produce nanocrystalline materials by mechanisms such as grain fragmentation, dynamic recovery, and nonrepresentationalal re-crystallization 34. It is the only technology that transformed conventional macro-grained metals directly into nanocrystalline materials without the need of potentially hazardous nano-sized powders. This is achieved by introducing very high shear deformations into the material under place hydrostatic pressure. Two of the most commonly used methods are hig h-pressure torsion and ECAE 35. In the study of the effect of ECAE on the microstructure of nanocrystalline copper, Dalla Torre et al 36 observed that the grains rifle more equi-axial and randomly preference as the number of passes increases, as shown in Figure 2.5Figure 2.5 Microstructure of ECAE copper subjected to (a) 1 passes (b) 2 passes (c) 4 passes (d) 8 passes (e) 12 passes and (f) 16 passes 362.2.2 Mechanical Behavior of nanocrystalline materialsDue to the small grain size and high volume fraction of grain boundaries, nanocrystalline materials exhibit significantly different properties and sort as compared to their microcrystalline counterpart. The structure and mechanical style of nanocrystalline materials has been the subject of a lot of researchers interests both experimentally 37-43 and theoretically 44-50. This section reviews the principal mechanical properties and behavior of nanocrystalline materials.2.2.2.1 Strength and ductilityRecent studies of nanocrystallin e metals have shown that there is a five to ten fold increases in the strength and hardness as compared to their microcrystalline raise 7, 36, 37, 51, 52. This increase in the strength is due to the comportment of grain boundaries impeding the nucleation and movement of flutters.Since decreasing grain boundary size increases the number of barrier and the meat of applied stress necessary to move a partitioning across a grain boundary, this resulted in a much higher yield strength. The opposite word relationship between grain size and strength is characterized by the Hall-Petch relationship 53, 54 as shown in equation (2.1).Eq (2.1)In equation (2.1), s is the mechanical strength, k is a material constant and d is the average grain size. Hence, nanocrystalline materials are expected to exhibit higher strength as compared to their microcrystalline counterpart. Figure 2.6 and Figure 2.7 show the summary of hardness and yield strength from tensile test that are reported in the lite rature. Indeed, hardness and yield strength of copper with a grain size of 10nm (3GPa) can be one order higher than their microcrystalline counterpart. To the larger specimens.Derivation from Hall-Petch relationship begins as the grain size approaches 30nm where the stresses needed to activate the dislocation multiplication via Frank-Read sources within the grains are too high and the plastic deformation is instead accommodated by grain boundaries sliding and migration.12. Furthermore, as the grain size reduces, the volume fraction of the grain boundaries and the triple points increases.Material properties will be more representative of the grain boundary activity 64 and this will resulting the strength to be antonymly proportional to grain size instead of square roots of the grain size as predicted by Hall Petch relation 65. Further reduction in the grain size will result in grain boundaries processes controlling the plastic deformation and reverse Hall-Petch effect, where the mat erials soften, will capture place.Although sample defects had been account for the earlier experimental bill of reverse Hall-Petch effect24, Swygenhoven et al 66 and Schiotz et al 47, using molecular simulation, was able to showed that nanocrystalline copper had the highest strength (about 2.3GPa ) at a grain size of 8nm and 10-15nm several(prenominal)ly. Conrad et al 67 pointed out that below this critical grain size, the mechanisms shifted to grain boundary-mediated from dislocation-mediated plasticity and this causes the material to get under ones skin dependent on strain rate, temperature, Taylor preference factor and aim of the type of dislocation.The yield stress of nanocrystalline copper was highly sensitive to strain rate even though it is a fcc materials. The strain rate sensitivity, m, in equation 2.2 a engineering parameter which measured the dependency of the strain rate and Figure 2.8 shows a summary of m as a function of grain size for copper specimen in the lite rature 51, 68-70. Due to high localized dislocation activities at the grain boundaries which results in intensify strain rate sensitivities in nanocrystalline materials, m increases drastically when the grain size is below 0.1 mm as shown in Figure 2.8.(2.2)Room temperature strain rate sensitivity was put to dependent on dislocation activities and grain boundaries diffusion 52, 71, 72. Due to the negligible lattice diffusion at room temperature, the rate throttle process for microcrystalline copper was the gliding dislocation to cutting through forest dislocation, resulting in low strain rate sensitivities.However, due to the increasing presence of obstacles such as grain boundaries for nanocrystalline materials, the rate modification process for smaller grain size was the interaction of dislocation and the grain boundaries, which is strain rate and temperature dependence. By considering the length scale of the dislocation and grain boundaries interaction, Cheng et al 52 proposed the next model for strain rate sensitivities. (2.3)z is the distance swept by the dislocation during activation, r is the dislocation density and a, a and b are the proportional factors. With this model, they will be able to predict higher strain rate sensitivities for nanocrystalline material produced by severe plastic deformation as compared to other technique. Since the twin boundaries in nanocrystalline or ultra fine grain copper served as a barriers for dislocation motion and nucleation which led to highly localized dislocations near the twin boundaries, the strain rate sensitivity of copper with high density of coherent twin boundaries was plunge to be higher than those without any twin boundaries 33. Lastly, the increase enhanced strain rate sensitivity in nanocrystalline copper had been credited for it increases in strength and ductility. For example, Valiev et al 60 credited the enhanced strain rate sensitivity of 0.16 for the high ductility.In addition to a strong depen dency on the strain rate, strength in nanocrystalline materials was also highly dependent on the temperature. Wang et al 73 observed that the yield strength for ultra fine grain copper with a grain size of 300nm increases from approximately 370MPa to 500MPa when the temperature reduces from room temperature to 77k. The authors attributed this increase in yield strength due to the absence of additional thermal deformation processes at 77k. This is consistent with Huang et al 74 ceremonial occasion where the temperature dependence of nanocrystalline copper with an increase in hardness of nanocrystalline copper with lowering the temperature is notedDuctility is another important characteristic of nanocrystalline materials. In microcrystalline materials, a reduction in grain size will increase the ductility due to the presence of grain boundaries acting as effective barriers to the propagation of micro-cracks75. However, nanocrystalline copper showed a lower strain to failure than that of their microcrystalline counterparts and this lacks in ductility was attributed to the presence of processing defects 76.Recent advanced in processing of nanocrystalline materials offer materials with passably good ductility in additional to ultra-high strength. Lu et al 10 reported that nanocrystalline copper with minimal flaw produced via electro-deposition had an elongation to fracture of 30%. Furthermore, Youssef et al 77 observed a 15.5% elongation to failure for defect free nanocrystalline copper produced via mechanical milling. Hence, it was possible for nanocrystalline copper to be both strong and ductile if the processing artifacts are minimized.The failure are usually consists of dimples several time larger than their grain size was normally found on the failure morphology of nanocrystalline materials and Kumar et al 78 presented the following model for initiation and hence the eventual failure of nanocrystalline materials. Furthermore, the presence of shear region was found to be due to shear localization since the ratio of strain hardening rate to prevailing stress was usually small 79, 80.Figure 2.9 Schematic illustration of fracture in nanocrystalline material postulated by Kumar et al 782.2.2.2 locomoteNanocrystalline materials are expected to creep during room temperature. This is because Due to the higher fraction of grain boundaries and triple junctions, self diffusivity of nanocrystalline material had been shown to increase by an order of trinity as compared to microcrystalline copper 81. Since creep behavior was dependent on grain size and diffusivity, with creep rate increases with an increase in diffusivity or a decrease in grain size, the creep temperature for nanocrystalline copper was known to be a small fraction of melting temperature (about 0.22 of its melting points). Furthermore, since creep had always been cited as one of the reason for grain size softening in nanocrystalline materials, creeps were other important mechanical properties of nanocrystalline materials that had been gaining a lot of researchers attention.Due to the high volume fraction of grain boundaries and enhanced diffusivity rateModel for Predicting Fatigue Life of NanomaterialsModel for Predicting Fatigue Life of NanomaterialsIntroductionIn the past, the primary function of micro-systems packaging was to provide input/output (I/O) connections to and from integrated circuits (ICs) and to provide interconnection between the components on the system board level while physically supporting the electronic device and protecting the assembly from the environment.In order to increase the functionality and the miniaturization of the current electronic devices, these IC devices have not only incorporated more transistors but have also included more active and passive components on an individual chip. This has resulted in the emerging trend of a new convergent system1Currently, there are three main approaches to achieving these convergent system s, namely the system-on-chip (SOC), system-in-package (SIP) and system on package (SOP). SOC seeks to integrate numerous system functions on one silicon chip. However, this approach has numerous fundamental and economical limitations which include high fabrication costs and integration limits on wireless communications, which due to inherent losses of silicon and size restriction.SIP is a 3-D packaging approach, where vertical stacking of multi-chip modules is employed. Since all of the ICs in the stack are still limited to CMOS IC processing, the fundamental integration limitation of the SOC still remains. SOP on the other hand, seeks to achieve a highly integrated microminiaturized system on the package using silicon for transistor integration and package for RF, digital and optical integration1 IC packaging is one of the key enabling technologies for microprocessor performance.As performance increases, technical challenges increase in the areas of agency delivery, heat removal, I/O density and thermo-mechanical reliability. These are the most difficult challenges for improving performance and increasing integration, along with decreasing manufacturing cost.Chip-to-package interconnections in microsystems packages serve as electrical interconnections but often fail by mechanisms such as fatigue and creep. Furthermore, driven by the need for increase the system functionality and decrease the feature size, the International Technology Roadmap for Semi-conductors (ITRS) has predicted that integrated chip (IC) packages will have interconnections with I/O pitch of 90 nm by the year 2018 2. Lead-based solder materials have been used for interconnections in flip chip technology and the surface mount technology for many decades.The traditional lead-based and lead-free solder bumps will not satisfy the thermal mechanical requirement of these fine pitches interconnects. These electronic packages, even under normal operating conditions, can reach a temperature as high as 150C. Due to differences in the coefficient of thermal expansion of the materials in an IC package, the packages will experience significant thermal strains due to the mismatch, which in turn will cause lead and lead-free solder interconnections to fail prematurely.Aggarwal et al 3 had modeled the stress experienced by chip to package interconnect. In his work, he developed interconnects with a height of 15 to 50 micrometre on different substrate using classic beam theory. Figure 1 shows the schematic of his model and a summary of some of his results.Although compliant intrerconect could reduces the stress experienced by the interconnect, it is still in sufficient. Chng et al. 4 performed a parametric study on the fatigue life of a solder column for a pitch of 100micrometre using a macro-micro approach. In her work, she developed models of a solder column/bump with a pad size of 50micrometre and senior high school of 50 micrometre to 200 micrometre. Table I shows a summary of so me of her results.Table 1.1 Fatigue life estimation of solder columnchip oppressiveness (micrometre)250640640640board CTE (ppm/K)1818105solder column height (micrometre)Fatigue life estimation/cycle)5081N.A171323710015027276312415013431518440520074382735772It can be seen from Table 1.1 that the fatigue lives of all solder columns are extremely short. obscure from the 5ppm/K board where there is excellent CTE matching, the largest fatigue life of the solder column is only about 518 cycles. As expected, the fatigue life increases significantly when the board CTE decreases from 18ppm/K to 10ppm/K and as the height increases from 50micrometre to 200micrometre.This is mainly due to the large strain induced by the thermal mismatch as shown in Figure 1.2.The maximum inelastic principal strain was about 0.16 which exceeds the maximum strain that the material can support. Although the fatigue life of the chip to package interconnection can be increases by increasing the interconnects heigh t, it will not be able to meet the high frequency electrical requirements of the future IC where they need to be operating at a high frequencies of 10-20 GHz and a signal bandwidth of 20 Gbps,By definition, nanocrystalline materials are materials that have grain size less than 100nm and these materials are not new since nanocrystalline materials have been observed in several naturally-occurring specimens including seashells, bone, and tooth enamel 5, 6. However, the nanocrystalline materials have been attracting a lot of research interest due to its superior mechanical and electrical properties as compared to the coarse-grained counterpart.For example, the nano-crystalline copper has about 6 times the strength of bulk copper 7. Furthermore, the improvement in the mechanical properties due to the reduction in grain size has been well-documented. Increase in strength due to the reduction in grain-size is predicted by the Hall-Petch relationship which has also been confirmed numericall y by Swygenhoven et al 8 and was first demonstrated experimentally by Weertman 9.The implantation of nanocrystalline copper as interconnect materials seems to be feasible from the processing viewpoint too. Copper has been used as interconnects materials since 1989 whereas nano-copper has also been widely processed using electroplating and other severe plastic deformation techniques in the past few years. For instance, Lu et al. 10 have reported electroplating of nano-copper with grain size less than 100 nm and electrical conductivity comparable to microcrystalline copper. Furthermore, Aggarwal et al 11 have demonstrated the feasibility of using electrolytic plating processes to deposit nanocrystalline nickel as a back-end wafer compatible process. However, there are certain challenges regarding implantation of nanocrystalline copper as interconnects materials.As discussed above, nanocrystalline copper have a high potential of being used as the next generation interconnect for electr onic packaging. However, it is vital to understand their material properties, deformation mechanisms and microstructures stability. Although the increase in strength due to the Hall-Petch relationship which has also been confirmed numerically and experimentally by Weertman 9, the improvement in the fatigue properties is not well documented and no model has been established to predict/characterize these nano materials in interconnection application conflicting results regarding the fatigue properties have also been reported. Kumar et al 12 reported that for nano-crystalline and ultra-fine crystalline Ni, although there is an increase in tensile stress range and the endurance limit, the crack growth rate also increases.However, Bansal et al. 7 reported that with decreasing grain size, the tensile stress range increases but the crack growth rate decreases substantially at the same cyclic stress intensity range. Thus, nanostructured materials can potentially provide a solution for the r eliability of low pitch interconnections. However, the fatigue resistance of nanostructured interconnections needs to be further investigated.Since grain boundaries in polycrystalline material increases the nub energy of the system as compare to perfect single crystal, it will resulted in a driving force to reduce the overall grain boundary area by increasing the average grain size. In the case of nanocrystalline materials which have a high volume fraction of grain boundaries, there is a huge driving force for grain to growth and this presented a presents a significant obstacle to the processing and use of nanocrystalline copper for interconnect applications.Millet et al 13 have shown, though a series of systematic molecular dynamics simulations, grain growth in bulk nanocrystalline copper during annealing at constant temperature of 800K can be impeded with dopants segregated in the grain boundaries regions. However, it has been observed that stress can trigger grain growth in nano crystalline materials 14 and there is no literature available on impeding stress assisted grain growth. There is an impending need to investigate the impediment to grain growth caused by the dopant during fatigue/stress assisted grain growthDissertation ObjectivesThe goal of present project is to develop a model for the fatigue resistance of nano-materials that have been shown to have superior fatigue resistance. Accordingly, the following research objectives are proposed.Develops a model for predicting fatigue life of nanostructured chip-to-package copper interconnectionsDevelops a fundamental understanding on the fatigue behavior of nanocrystalline copper for interconnect applicationAddresses the issue on the stability of nanocrystalline materials undergoing cyclic loadingOverview of the ThesisThe thesis is organized so that past research on nanocrystalline materials forms the basis of the understanding and new knowledge discovered in this research. Chapter 2 reviews much of the p ertinent literature regarding nanocrystalline materials, including synthesis, deformation mechanisms, and grain growth.Chapter 3 describes a detailed overview of the technical aspects of the molecular dynamics simulation method including inter-atomic potentials, time integration algorithms, the NVT NPT, and NEPT ensembles, as well as periodic boundary conditions and neighbor lists. accommodate in this chapter is the algorithms for creating nanocrystallinematerials used in this dissertations.. Chapter 4 describes the simulation procedure designed to investigate and develop the long crack growth analysis. The results of the long crack growth analysis will be presented at the end of Chapter 4. Chapter 5 presents the result and discussion on mechanical behavior of single and nanocrystalline copper subjected to monotonic and cyclic loading whereas Chapter 6 presents the result and discussion on the impediment to grain growth caused by the dopant during fatigue/stress assisted grain grow th. Finally, conclusions and recommendations for future work are presented in Chapter 5.Chapter 2This chapter offers an expanded summary of the literature published with regards to the fabrication methods, characterization, and properties of nanocrystalline materials in addition to a description of existing interconnect technology.2.1 Off-Chip unite TechnologiesChip-to-package interconnections in microsystems packages serve as electrical interconnections but they will often failed by mechanisms such as fatigue and creep. Furthermore, driven by the need for increase the system functionality and decrease the feature size, the International Technology Roadmap for Semi-conductors (ITRS) has predicted that interconnections of integrated chip (IC) packages will have a I/O pitch of 90 nm by the year 2018 2.The International Technology Roadmap for Semiconductors (ITRS) roadmap is a roadmap that semiconductor industry closely follows closely and its projects the need for several technology generations. The package must be capable of meeting these projections in order for it to be successful. This section reviews some of the current interconnect technology.Wire bonding 15 as shown in Figure 2.1, is largely considered as one of the most simple, cost-effective and flexible interconnect technology. The devices on the silicon die are (gold or aluminum) wire bonded to electrically connect from the chip to the wire bond pads on the periphery. However, the disadvantages of wire bonding are the slow rate, large pitch and long interconnect length and hence this will not be suitable for high I/O application.Instead of wires in the wire bonding, tape automated bonding (TAB) is an interconnect technology using a prefabricated perforated polyimide film, with copper leads between chip and substrate. The advantage of this technology is the high throughput and the high lead count. However, it is limited by the high initial costs for tooling.An chute(a) to peripheral interconnect te chnology is the area-array solution, as shown in Figure 2.3, that access the unused area by using the area under the chip. In area-array packaging, the chip has an array of solder bumps that are joined to a substrate. Under-fill is then fills the gap between the chip and substrate to enhance mechanical adhesion. This technology gives the highest packaging density methods and best electrical characteristics of all the avaiable interconnection technology. However, not only is its initial cost is high, it requires a very demanding technology to establish and operate.With the need for higher I/O density, compliant interconnects have been developed to satisfy the mechanical requirements of high performance micron sized interconnects. The basic idea is to reduce shear stress experienced by the interconnects through increasing their height or decreasing of its shear modulus (i.e. increases in their compliant) and hence the name compliant interconnects. Some of recent research in compliant interconnects include Tesseras Wide Area Vertical Expansion, Form Factors Wire on Wafer and Georgia Institute of Technologys Helix interconnects 17-19 as shown in Figure 2.4.Although compliant interconnects can solve the problem of mechanical reliability issue, they are done at the expense of the electrical performance. Since there is a need to reduce the packages parasitic through a decrease line delays, there is a need to minimize the electrical connection length in order to increase the system working frequency. Hence, compliant interconnect may not meet the high electrical frequency requirements of future devices.Figure 2.4 (a) Wide Area Vertical Expansion, (b) Wire on Wafer and (c) G-Helix 17-19Lead and lead-free solders typically fail mechanical when scaled down to less than to a pitch of 100 mm. Compliant interconnections, on the other hand, do not meet the high frequency electrical requirements. The Microsystems Packaging Research Center at Georgia institute of Technology ha d demonstrated the feasibility of using re-workable nanostructure interconnections. Aggarwal et al 20 had show that nanostructured nickel interconnections, through a Flip Chip test vehicle, was able to improve the mechanical reliability while maintaining the shortest electrical connection length. However, the main disadvantages of this method was the significant signal loss at high frequency signal of nanocrystalline nickel 21.As discussed above, nanostructure interconnects technology is the most promising interconnect technology to best meet the stringent mechanical and electrical requirement of next generation devices. However, there is a need of an alternate materials and a sensible choice of materials in this case would be nanocrystalline copper for its high strength material with superior electrical conductivity.Hence, it would be beneficial to use nanocrystalline-copper as material for the nanostructure interconnects. Due to the tendency for the grain to grow, there is a need to stabilize the grain growth in nanocrystalline copper before using it could be considered as a potential candidate for nanostructure interconnect.2.2 Nanocrystalline materialNanocrystalline materials are polycrystalline materials with an average grain size of less than 100 nm 22. Over the past decade , new nanocrystalline or nanostructured materials with key microstructural length scales on the order of a few tens of nanometers has been gaining a lot of interest in the material science research society.This is mainly due to its unique and superior properties, as compared to their microcrystalline counterparts which includes increased strength 22 and wear resistance 23. These unique properties are due to the large volume fraction of atoms at or near the grain boundaries. As a result, these materials have unique properties that are representative of both the grain boundary surface characteristics and the bulk.Recent advances in synthesis and processing methodology for producing nano crystalline materials such as inert gas condensation 24, mechanical milling 25, 26, electro-deposition 27, and severe plastic deformation 28 have made it possible to produce sufficient nanocrystalline materials for small scale application.2.2.1 SynthesisInert gas condensation, the first method used to synthesis bulk nanocrystalline 29, consists of evaporating a metal inside a high-vacuum chamber and then backfilling the chamber with inert gas 30. These evaporated metal atoms would then collide with the gas atoms, causing them to lose kinetic energy and condenses into powder of small nano-crystals. These powders are then compacted under high pressure and vacuum into nearly fully dense nanocrystalline solids.The grain size distribution obtained from this method is usually very narrow. However, the major draws back of this method are its high porosity levels and imperfection bonding. Grain coarsening also occurs due to the high temperature during the compaction stage 31.Mechanical mill ing consists of heavy cyclic deformation in powders until the final composition of the powders corresponds to a certain percentages of the respective initial constituents 25, 26. A wide grain size distribution is obtained by this method. This technique is a popular method to prepare nanocrystalline materials because of its applicability to any material and simplicity. However, their main drawback includes contamination and grain coarsening during the consolidation stage.Electro-deposition consists of using electrical current to reduce cations of a desired material from a electrolyte solution and coating a conductive object on the substrate. Electro-deposition has many advantages over processing techniques and this includes its applicability to a wide variety of materials, low initial capital investment requirements and porosity-free blameless products without a need for consolidation processing 27. Furthermore, Shen et al. 32 and Lu et al.33 had recently show that the right electro -deposition condition can produce a highly twinned structure which leads to enhanced ductility. The main drawback of this method is it is the difficulty to achieve high purity.Severe plastic deformation, such as high-pressure torsion, equal channel angular riddance (ECAE), continuous confined shear straining and accumulative roll-bonding, uses extreme plastic straining to produce nanocrystalline materials by mechanisms such as grain fragmentation, dynamic recovery, and geometric re-crystallization 34. It is the only technology that transformed conventional macro-grained metals directly into nanocrystalline materials without the need of potentially hazardous nano-sized powders. This is achieved by introducing very high shear deformations into the material under overlying hydrostatic pressure. Two of the most commonly used methods are high-pressure torsion and ECAE 35. In the study of the effect of ECAE on the microstructure of nanocrystalline copper, Dalla Torre et al 36 observed t hat the grains become more equi-axial and randomly orientation as the number of passes increases, as shown in Figure 2.5Figure 2.5 Microstructure of ECAE copper subjected to (a) 1 passes (b) 2 passes (c) 4 passes (d) 8 passes (e) 12 passes and (f) 16 passes 362.2.2 Mechanical Behavior of nanocrystalline materialsDue to the small grain size and high volume fraction of grain boundaries, nanocrystalline materials exhibit significantly different properties and behavior as compared to their microcrystalline counterpart. The structure and mechanical behavior of nanocrystalline materials has been the subject of a lot of researchers interests both experimentally 37-43 and theoretically 44-50. This section reviews the principal mechanical properties and behavior of nanocrystalline materials.2.2.2.1 Strength and ductilityRecent studies of nanocrystalline metals have shown that there is a five to ten fold increases in the strength and hardness as compared to their microcrystalline state 7, 36, 37, 51, 52. This increase in the strength is due to the presence of grain boundaries impeding the nucleation and movement of dislocations.Since decreasing grain boundary size increases the number of barrier and the tote up of applied stress necessary to move a dislocation across a grain boundary, this resulted in a much higher yield strength. The inverse relationship between grain size and strength is characterized by the Hall-Petch relationship 53, 54 as shown in equation (2.1).Eq (2.1)In equation (2.1), s is the mechanical strength, k is a material constant and d is the average grain size. Hence, nanocrystalline materials are expected to exhibit higher strength as compared to their microcrystalline counterpart. Figure 2.6 and Figure 2.7 show the summary of hardness and yield strength from tensile test that are reported in the literature. Indeed, hardness and yield strength of copper with a grain size of 10nm (3GPa) can be one order higher than their microcrystalline counterpart. To the larger specimens.Derivation from Hall-Petch relationship begins as the grain size approaches 30nm where the stresses needed to activate the dislocation multiplication via Frank-Read sources within the grains are too high and the plastic deformation is instead accommodated by grain boundaries sliding and migration.12. Furthermore, as the grain size reduces, the volume fraction of the grain boundaries and the triple points increases.Material properties will be more representative of the grain boundary activity 64 and this will resulting the strength to be inversely proportional to grain size instead of square roots of the grain size as predicted by Hall Petch relation 65. Further reduction in the grain size will result in grain boundaries processes controlling the plastic deformation and reverse Hall-Petch effect, where the materials soften, will sequester place.Although sample defects had been account for the earlier experimental observation of reverse Hall-Petch effect24, S wygenhoven et al 66 and Schiotz et al 47, using molecular simulation, was able to showed that nanocrystalline copper had the highest strength (about 2.3GPa ) at a grain size of 8nm and 10-15nm respectively. Conrad et al 67 pointed out that below this critical grain size, the mechanisms shifted to grain boundary-mediated from dislocation-mediated plasticity and this causes the material to become dependent on strain rate, temperature, Taylor orientation factor and presence of the type of dislocation.The yield stress of nanocrystalline copper was highly sensitive to strain rate even though it is a fcc materials. The strain rate sensitivity, m, in equation 2.2 a engineering parameter which measured the dependency of the strain rate and Figure 2.8 shows a summary of m as a function of grain size for copper specimen in the literature 51, 68-70. Due to high localized dislocation activities at the grain boundaries which results in enhanced strain rate sensitivities in nanocrystalline materi als, m increases drastically when the grain size is below 0.1 mm as shown in Figure 2.8.(2.2)Room temperature strain rate sensitivity was found to dependent on dislocation activities and grain boundaries diffusion 52, 71, 72. Due to the negligible lattice diffusion at room temperature, the rate limiting process for microcrystalline copper was the gliding dislocation to cutting through forest dislocation, resulting in low strain rate sensitivities.However, due to the increasing presence of obstacles such as grain boundaries for nanocrystalline materials, the rate limiting process for smaller grain size was the interaction of dislocation and the grain boundaries, which is strain rate and temperature dependence. By considering the length scale of the dislocation and grain boundaries interaction, Cheng et al 52 proposed the following model for strain rate sensitivities. (2.3)z is the distance swept by the dislocation during activation, r is the dislocation density and a, a and b are the proportional factors. With this model, they will be able to predict higher strain rate sensitivities for nanocrystalline material produced by severe plastic deformation as compared to other technique. Since the twin boundaries in nanocrystalline or ultra fine grain copper served as a barriers for dislocation motion and nucleation which led to highly localized dislocations near the twin boundaries, the strain rate sensitivity of copper with high density of coherent twin boundaries was found to be higher than those without any twin boundaries 33. Lastly, the increase enhanced strain rate sensitivity in nanocrystalline copper had been credited for it increases in strength and ductility. For example, Valiev et al 60 credited the enhanced strain rate sensitivity of 0.16 for the high ductility.In addition to a strong dependency on the strain rate, strength in nanocrystalline materials was also highly dependent on the temperature. Wang et al 73 observed that the yield strength for ultra f ine grain copper with a grain size of 300nm increases from approximately 370MPa to 500MPa when the temperature reduces from room temperature to 77k. The authors attributed this increase in yield strength due to the absence of additional thermal deformation processes at 77k. This is consistent with Huang et al 74 observation where the temperature dependence of nanocrystalline copper with an increase in hardness of nanocrystalline copper with lowering the temperature is notedDuctility is another important characteristic of nanocrystalline materials. In microcrystalline materials, a reduction in grain size will increase the ductility due to the presence of grain boundaries acting as effective barriers to the propagation of micro-cracks75. However, nanocrystalline copper showed a lower strain to failure than that of their microcrystalline counterparts and this lacks in ductility was attributed to the presence of processing defects 76.Recent advanced in processing of nanocrystalline mate rials offer materials with more or less good ductility in additional to ultra-high strength. Lu et al 10 reported that nanocrystalline copper with minimal flaw produced via electro-deposition had an elongation to fracture of 30%. Furthermore, Youssef et al 77 observed a 15.5% elongation to failure for defect free nanocrystalline copper produced via mechanical milling. Hence, it was possible for nanocrystalline copper to be both strong and ductile if the processing artifacts are minimized.The failure are usually consists of dimples several time larger than their grain size was normally found on the failure morphology of nanocrystalline materials and Kumar et al 78 presented the following model for initiation and hence the eventual failure of nanocrystalline materials. Furthermore, the presence of shear region was found to be due to shear localization since the ratio of strain hardening rate to prevailing stress was usually small 79, 80.Figure 2.9 Schematic illustration of fracture i n nanocrystalline material postulated by Kumar et al 782.2.2.2 creepNanocrystalline materials are expected to creep during room temperature. This is because Due to the higher fraction of grain boundaries and triple junctions, self diffusivity of nanocrystalline material had been shown to increase by an order of three as compared to microcrystalline copper 81. Since creep behavior was dependent on grain size and diffusivity, with creep rate increases with an increase in diffusivity or a decrease in grain size, the creep temperature for nanocrystalline copper was known to be a small fraction of melting temperature (about 0.22 of its melting points). Furthermore, since creep had always been cited as one of the reason for grain size softening in nanocrystalline materials, creeps were other important mechanical properties of nanocrystalline materials that had been gaining a lot of researchers attention.Due to the high volume fraction of grain boundaries and enhanced diffusivity rate